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| Class-D Audio Power Amplifier ADAU1590 FEATURES Integrated stereo modulator and power stage 0.005% THD + N 101 dB dynamic range PSRR >55 dB RDS-ON < 0.3 (per transistor) Efficiency > 90% (8 ) EMI-optimized modulator On/off-mute pop-noise suppression Short-circuit protection Overtemperature protection GENERAL DESCRIPTION The ADAU1590 is a 2-channel, bridge-tied load (BTL) switching audio power amplifier with an integrated - modulator. The modulator accepts an analog input signal and generates a switching output to drive speakers directly. A digital, microcontroller-compatible interface provides control of reset, mute and PGA gain as well as output signals for thermal and overcurrent error conditions. The output stage can operate from supply voltages ranging from 9 V to 15 V. The analog modulator and digital logic operate from a 3.3 V supply. APPLICATIONS Flat panel televisions PC audio systems Mini-components FUNCTIONAL BLOCK DIAGRAM PGA0 PGA1 PVDD AINL PGA A1 A2 OUTL+ PGND PVDD B1 SLC_TH SLICER - MODULATOR B2 OUTL- PGND PVDD C1 C2 AINR PGA OUTR+ PGND PVDD PGA0 AVDD PGA1 D1 D2 OUTR- PGND LEVEL SHIFT AND DEAD TIME CONTROL VREF AGND DVDD DGND VOLTAGE REFERENCE fCLK/2 CLOCK OSCILLATOR MODE CONTROL LOGIC TEMPERATURE OVERCURRENT PROTECTION XTI XTO MO/ST STDN MUTE ERR OTW Figure 1. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2007 Analog Devices, Inc. All rights reserved. 06673-001 ADAU1590 ADAU1590 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Audio Performance ...................................................................... 3 DC Specifications ......................................................................... 4 Power Supplies .............................................................................. 4 Digital I/O ..................................................................................... 4 Digital Timing............................................................................... 5 Absolute Maximum Ratings............................................................ 6 Thermal Resistance ...................................................................... 6 ESD Caution.................................................................................. 6 Pin Configuration and Function Descriptions............................. 7 Typical Performance Characteristics ............................................. 9 Theory of Operation ...................................................................... 15 Overview...................................................................................... 15 Modulator.................................................................................... 15 Slicer............................................................................................. 15 Power Stage ................................................................................. 16 Gain.............................................................................................. 16 Protection Circuits ..................................................................... 16 Thermal Protection.................................................................... 16 Overcurrent Protection ............................................................. 16 Undervoltage Protection ........................................................... 17 Clock Loss Detection ................................................................. 17 Automatic Recovery from Protections .................................... 17 MUTE and STDN ...................................................................... 17 Power-Up/Power-Down Sequence .......................................... 18 DC Offset and Pop Noise .......................................................... 19 Selecting Value for CREF and CIN ............................................... 19 Mono Mode................................................................................. 19 Power Supply Bypassing ............................................................ 19 Clock ............................................................................................ 20 Applications Information .............................................................. 21 Outline Dimensions ....................................................................... 23 Ordering Guide........................................................................... 23 REVISION HISTORY 5/07--Revision 0: Initial Version Rev. 0 | Page 2 of 24 ADAU1590 SPECIFICATIONS AVDD = DVDD = 3.3 V, PVDD = 12 V, ambient temperature = 25C, load impedance = 6 , clock frequency = 24.576 MHz, measurement bandwidth = 20 Hz to 20 kHz, unless otherwise noted. AUDIO PERFORMANCE Table 1. Parameter OUTPUT POWER 1 Min Typ 7 9 9 11.5 12.5 15.5 87 0.28 0.25 135 150 6 5.1 1.0 0.5 0.25 0.125 0.005 101 101 -90 17 23 29 35 65 83 130 230 57 Max Unit W W W W W W % C C A V VRMS VRMS VRMS VRMS % dB dB dB dB dB dB dB PVDD = 12 V, 6 V V V V dB Test Conditions/Comments 1 kHz 1% THD + N, 8 10% THD + N , 8 1% THD + N, 6 10% THD + N, 6 1% THD + N , 4 10% THD + N , 4 @ 12 W, 6 @ TCASE = 25C @ 100 mA @ 100 mA Die temperature Die temperature Peak current Full-scale output @ 1% THD + N PGA gain = 0 dB PGA gain = 6 dB PGA gain = 12 dB PGA gain = 18 dB 1 kHz, POUT = 1 W, PGA gain = 0 dB A-weighted, referred to 1% THD + N output A-weighted, measured with -60 dBFS input @ full-scale output voltage, 1% THD + N, 1 kHz PVDD = 12 V, 6 EFFICIENCY RDS-ON Per High-Side Transistor Per Low-Side Transistor THERMAL CHARACTERISTICS Thermal Warning Active 2 Thermal Shutdown Active OVERCURRENT SHUTDOWN ACTIVE PVDD UNDERVOLTAGE SHUTDOWN INPUT LEVEL FOR FULL-SCALE OUTPUT 5 TOTAL HARMONIC DISTORTION + NOISE (THD+N) SIGNAL-TO-NOISE RATIO (SNR) DYNAMIC RANGE (DNR) CROSSTALK (LEFT TO RIGHT OR RIGHT TO LEFT) AMPLIFIER GAIN PGA = 0 dB PGA = 6 dB PGA = 12 dB PGA = 18 dB OUTPUT NOISE VOLTAGE PGA = 0 dB PGA = 6 dB PGA = 12 dB PGA = 18 dB POWER SUPPLY REJECTION RATIO (PSRR) 1 2 99 99 20 Hz to 20 kHz, 1.2 V p-p ripple, inputs accoupled to AGND Output powers above 12 W at 4 and above 18 W at 6 are not continuous and are thermally limited by the package dissipation. Thermal warning flag is for indication of device TJ reaching close to shutdown temperature. Rev. 0 | Page 3 of 24 ADAU1590 DC SPECIFICATIONS Table 2. Parameter INPUT IMPEDANCE OUTPUT DC OFFSET VOLTAGE Min Typ 20 3 Max Unit k mV Test Conditions/Comments AINL/AINR POWER SUPPLIES Table 3. Parameter ANALOG SUPPLY VOLTAGE (AVDD) DIGITAL SUPPLY VOLTAGE (DVDD) POWER TRANSISTOR SUPPLY VOLTAGE (PVDD) POWER-DOWN CURRENT AVDD DVDD PVDD MUTE CURRENT AVDD DVDD PVDD OPERATING CURRENT AVDD DVDD PVDD Min 3.0 3.0 9 Typ 3.3 3.3 12 6 0.14 0.06 13 1.8 4.5 13 2.7 34 Max 3.6 3.6 15 60 0.24 0.25 20 3.2 8 30 4 65 Unit V V V A mA mA MUTE held low mA mA mA STDN and MUTE held high, no input mA mA mA Test Conditions/Comments STDN held low DIGITAL I/O Table 4. Parameter INPUT VOLTAGE Input Voltage High Input Voltage Low OUTPUT VOLTAGE Output Voltage High Output Voltage Low LEAKAGE CURRENT ON DIGITAL INPUTS Min 2 0.8 2 0.4 10 Typ Max Unit V V V V A @ 2 mA @ 2 mA Test Conditions/Comments Rev. 0 | Page 4 of 24 ADAU1590 DIGITAL TIMING Table 5. Parameter tWAIT tINT tHOLD tOUTx+/OUTx- SW tOUTx+/OUTx- MUTE 1 2 Min 0.01 1 101 Typ 1000 2 650 250 3 200 200 Unit ms ms s s s Test Conditions/Comments Wait time for unmute Internal mute time Wait time for shutdown Time delay after MUTE held high until output starts switching Time delay after MUTE held low until output stops switching tWAIT MIN and tHOLD MIN are the minimum times for fast turn-on and do not guarantee pop-and-click suppression. tWAIT TYP is the recommended value for minimum pop and click during the unmute of the amplifier. The recommended value is 1 sec. It is calculated using the input coupling capacitor value and the input resistance of the device. See the Power-Up/Power-Down Sequence section. 3 tHOLD TYP is the recommended value for minimum pop and click during the mute of the amplifier. STDN INTERNAL MUTE tINT tHOLD MIN tWAIT MIN MUTE OUTx+/OUTx- NOTES 1. INTERNAL MUTE IS INTERNAL TO CHIP. 06673-002 Figure 2.Timing Diagram (Minimum) STDN INTERNAL MUTE MUTE OUTx+/OUTx- tINT tHOLD TYP tWAIT TYP NOTES 1. INTERNAL MUTE IS INTERNAL TO CHIP. Figure 3. Timing Diagram (Typical) Rev. 0 | Page 5 of 24 06673-003 tOUTx+/OUTx- SW tOUTx+/OUTx- MUTE ADAU1590 ABSOLUTE MAXIMUM RATINGS Table 6. Parameter DVDD to DGND AVDD to AGND PVDD to PGND1 MUTE/STDN Inputs Operating Temperature Range Storage Temperature Range Maximum Junction Temperature Lead Temperature Soldering (10 sec) Vapor Phase (60 sec) Infrared (15 sec) 1 THERMAL RESISTANCE Rating -0.3 V to +3.6 V -0.3 V to +3.6 V -0.3 V to +20.0 V DGND - 0.3 V to DVDD + 0.3 V -40C to +85C -65C to +150C 150C JA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Table 7. Thermal Resistance Package Type LFCSP-48 TQFP-48 1 2 JA1 24.6 24.7 JC1, 2 2.0 1.63 JB 8.05 11 JT 0.18 0.8 Unit C/W C/W With exposed pad (ePAD) soldered to 4-layer JEDEC standard PCB. Through the bottom (ePAD) surface. 260C 215C 220C ESD CAUTION Includes any induced voltage due to inductive load. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. 0 | Page 6 of 24 ADAU1590 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 48 47 46 45 44 43 42 41 40 39 38 37 PGND PGND PVDD PVDD PVDD PVDD PVDD PVDD PVDD PVDD PGND PGND OUTL- 1 OUTL- 2 OUTL- 3 OUTL+ 4 OUTL+ 5 OUTL+ 6 TEST1 7 TEST0 8 ERR 9 OTW 10 MO/ST 11 TEST3 12 PIN 1 INDICATOR ADAU1590 TOP VIEW (Not to Scale) 36 35 34 33 32 31 30 29 28 27 26 25 OUTR- OUTR- OUTR- OUTR+ OUTR+ OUTR+ TEST13 TEST12 AINR AINL TEST9 TEST8 NOTES 1. EPAD NOT SHOWN AND INTERNALLY CONNECTED TO PGND, DGND, AND AGND FOR TQFP-48. 2. EPAD NOT SHOWN AND INTERNALLY CONNECTED TO PGND AND DGND FOR LFCSP-48. PGA1 PGA0 MUTE STDN XTI XTO DGND DVDD AVDD AGND VREF SLC_TH 13 14 15 16 17 18 19 20 21 22 23 24 Figure 4. Pin Configuration Table 8. Pin Function Descriptions Pin. Number 1, 2, 3 4, 5, 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31, 32, 33 Mnemonic OUTL- OUTL+ TEST1 TEST0 ERR OTW MO/ST TEST3 PGA1 PGA0 MUTE STDN XTI XTO DGND DVDD AVDD AGND VREF SLC_TH TEST8 TEST9 AINL AINR TEST12 TEST13 OUTR+ Type 1 O O I I O O I I I I I I I O P P P P I I I I I I I I O Description Output of High Power Transistors, Left Channel Negative Polarity. Output of High Power Transistors, Left Channel Positive Polarity. Reserved for Internal Use. Connect to DGND. Reserved for Internal Use. Connect to DGND. Error Indicator (Active Low, Open-Drain Output). Overtemperature Warning Indicator (Active Low Open-Drain Output). Mono/Stereo Mode Setting Pin for Stereo. Connect to DGND (for mono mode, connect to DVDD). Reserved for Internal Use. Connect to DVDD. Programmable Gain Amplifier Select, MSB. Programmable Gain Amplifier Select, LSB. Mute (Active Low Input). Shutdown/Reset Input (Active Low Input). Quartz Crystal Connection/External Clock Input. Quartz Crystal Connection/Clock Output. Digital Ground for Digital Circuitry. Internally connected to exposed pad (ePAD). Positive Supply for Digital Circuitry. Positive Supply for Analog Circuitry. (Can be tied to DVDD.) Analog Ground for Analog Circuitry. (See the notes in Figure 4 for connection to ePAD.) AVDD/2 Voltage Reference Connection for External Filter. Slicer Threshold Adjust. (Connect to AGND via a resistor for slicer operation.) Reserved for Internal Use. Connect to DGND. Reserved for Internal Use. Connect to DGND. Analog Input Left Channel. Analog Input Right Channel. Reserved for Internal Use. Connect to DGND. Reserved for Internal Use. Connect to DGND. Output of High Power Transistors, Right Channel Positive Polarity. Rev. 0 | Page 7 of 24 06673-004 ADAU1590 Pin. Number 34, 35, 36 37, 38, 47, 48 39, 40, 41, 42, 43, 44, 45, 46 1 Mnemonic OUTR- PGND PVDD Type 1 O P P Description Output of High Power Transistors, Right Channel Negative Polarity. Power Ground for High Power Transistors. Internally connected to EPAD. Positive Power Supply for High Power Transistors. I = input, O = output, P = power. Rev. 0 | Page 8 of 24 ADAU1590 TYPICAL PERFORMANCE CHARACTERISTICS -20 -30 -40 -20 -30 -40 -60 -70 -80 -90 THD -100 -110 06673-005 THD OR THD + N (dB) THD OR THD + N (dB) -50 -50 -60 -70 -80 -90 -100 -110 100m 1 10 06673-008 06673-010 06673-009 THD + N THD + N THD -120 10m 100m 1 10 -120 10m OUTPUT POWER (W) OUTPUT POWER (W) Figure 5. THD or THD + N vs. Output Power, 4 , PVDD = 9 V -20 -30 -40 Figure 8. THD or THD + N vs. Output Power, 4 , PVDD = 12 V -20 -30 -40 THD OR THD + N (dB) -60 -70 -80 -90 THD -100 -110 06673-006 THD OR THD + N (dB) -50 -50 -60 -70 -80 -90 THD -100 -110 THD + N THD + N -120 10m 100m 1 10 -120 10m 100m 1 10 OUTPUT POWER (W) OUTPUT POWER (W) Figure 6. THD or THD + N vs. Output Power, 6 , PVDD = 9 V -20 -30 -40 Figure 9. THD or THD + N vs. Output Power, 6 , PVDD = 12 V -20 -30 -40 THD OR THD + N (dB) -60 -70 -80 -90 -100 -110 06673-007 THD OR THD + N (dB) -50 -50 -60 -70 -80 -90 THD -100 -110 THD + N THD + N THD -120 10m 100m 1 10 -120 10m 100m 1 10 OUTPUT POWER (W) OUTPUT POWER (W) Figure 7. THD or THD + N vs. Output Power, 8 , PVDD = 9 V Figure 10. THD or THD + N vs. Output Power, 8 , PVDD = 12 V Rev. 0 | Page 9 of 24 ADAU1590 25 POWER LIMITED DUE TO PACKAGE DISSIPATION 20 0 -10 -20 -30 -40 4 0dBr = 9.5W OUTPUT POWER (W) -50 OUTPUT (dBr) 06673-011 15 6 10 8 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 0 2 4 6 8 10 12 14 16 18 20 06673-014 06673-016 06673-015 5 0 9 10 11 12 PVDD (V) 13 14 15 -160 FREQUENCY (kHz) Figure 11. Output Power vs. PVDD @ 0.1% THD + N 25 POWER LIMITED DUE TO PACKAGE DISSIPATION 4 Figure 14. FFT @ 1W, 6 , PVDD = 12 V, PGA = 0 dB, 1 kHz Sine 0 -10 -20 -30 -40 OUTPUT (dBr) 0dBr = 9.5W 20 OUTPUT POWER (W) 15 6 8 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 10 5 06673-012 0 9 10 11 12 PVDD (V) 13 14 15 0 2 4 6 8 10 12 14 16 18 20 FREQUENCY (kHz) Figure 12. Output Power vs. PVDD @ 1% THD + N 30 Figure 15. FFT @ -60 dBFS, 6 , PVDD = 12 V, PGA = 0 dB, 1 kHz Sine 0 -10 -20 4 -30 -40 6 8 OUTPUT (dBV) 25 OUTPUT POWER (W) 20 -50 -60 -70 -80 -90 -100 -110 -120 15 10 5 POWER LIMITED DUE TO PACKAGE DISSIPATION 9 10 11 12 PVDD (V) 13 14 15 06673-013 -130 -140 0 2 4 6 8 10 12 14 16 18 20 0 FREQUENCY (kHz) Figure 13. Output Power vs. PVDD @ 10% THD + N Figure 16. FFT No Input, 6 , PVDD = 12 V, PGA = 0 dB Rev. 0 | Page 10 of 24 ADAU1590 0 -10 -20 -30 -40 -50 OUTPUT (dBr) THD OR THD + N (dB) 0dBr = 9.5W 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 THD THD + N -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 0 2 4 6 8 10 12 14 16 18 20 22 06673-017 FREQUENCY (kHz) FREQUENCY (Hz) Figure 17. FFT @ 1 W, 6 , PVDD = 12 V, PGA = 0 dB, 19 kHz and 20 kHz Sine 0 -10 -20 -30 -40 OUTPUT (dB) Figure 20. THD or THD + N vs. Frequency @ 1 W, 4 , PVDD = 12 V, PGA = 0 dB 0 -10 -20 -30 THD OR THD + N (dB) -40 -50 -60 -70 -80 -90 THD + N -50 -60 -70 -80 -90 -100 -110 -120 20 100 1k FREQUENCY (Hz) LEFT TO RIGHT RIGHT TO LEFT -100 -110 06673-018 THD FREQUENCY (Hz) Figure 18. Crosstalk @ 1 W, 6 , PVDD = 12 V, PGA = 0 dB Figure 21. THD or THD + N vs. Frequency @ 1 W, 6 , PVDD = 12 V, PGA = 0 dB 0 -10 -20 -30 THD OR THD + N (dB) 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 LEFT TO RIGHT 100 1k FREQUENCY (Hz) 10k 06673-019 -40 OUTPUT (dB) -50 -60 -70 -80 -90 -100 -110 -120 20 RIGHT TO LEFT THD + N -110 -120 20 100 THD FREQUENCY (Hz) Figure 19. Crosstalk @ Full Scale, 6 , PVDD = 12 V, PGA = 0 dB Figure 22. THD or THD + N vs. Frequency @ 1 W, 8 , PVDD = 12 V, PGA = 0 dB Rev. 0 | Page 11 of 24 06673-022 1k 10k 06673-021 10k -120 20 100 1k 10k 06673-020 -160 -120 20 100 1k 10k ADAU1590 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 -1.2 -1.4 -1.6 -1.8 -2.0 20 90 80 70 EFFICIENCY (%) 60 50 40 30 20 10 06673-026 06673-028 06673-027 OUTPUT (dBr) 100 1k FREQUENCY (Hz) 10k 06673-023 0 POWER LIMITED DUE TO PACKAGE DISSIPATION 0 2 4 6 8 10 12 14 16 18 OUTPUT POWER (W) Figure 23. Frequency Response @ 1 W, 6 , PVDD = 12 V, PGA = 0 dB 37 35 33 31 EFFICIENCY (%) Figure 26. Efficiency vs. Output Power, 12 V, 4 100 PGA 18dB 90 80 29 GAIN (dB) PGA 12dB 70 60 50 40 30 20 27 25 23 21 19 17 15 20 100 1k FREQUENCY (Hz) PGA 0dB PGA 6dB 10 10k 06673-024 0 0 2 4 6 8 10 12 14 OUTPUT POWER (W) Figure 24. Gain vs. Frequency @ 1 W, 6 , PVDD = 12 V, 6 0 -10 -20 -30 PSRR (dB) Figure 27. Efficiency vs. Output Power,12 V, 6 100 90 80 70 EFFICIENCY (%) -40 -50 -60 -70 -80 -90 100 1k FREQUENCY (Hz) 10k 06673-025 60 50 40 30 20 10 0 0 2 4 6 8 10 12 -100 20 OUTPUT POWER (W) Figure 25. PSRR vs. Frequency, No Input Signal Ripple = 1.2 V p-p, PVDD = 12 V, 6 Figure 28. Efficiency vs. Output Power, 12 V, 8 Rev. 0 | Page 12 of 24 ADAU1590 10 POWER LIMITED DUE TO PACKAGE DISSIPATION 9 8 7 6 5 5 4 3 2 1 0 5 10 15 20 06673-029 PDISS MAX (W) 6 4 PDISS 3 2 1 0 POUT PER CHANNEL STEREO MODE TAMBIENT (C) Figure 29. Power Dissipation vs. Output Power, 12 V, 4 , Stereo Mode, Both Channels Driven 4 Figure 32. Power Dissipation Derating vs. Ambient Temperature 40 35 3 30 3 4 OUTPUT POWER (W) 25 20 15 10 5 6 8 PDISS 2 1 0 5 10 15 06673-030 POUT PER CHANNEL STEREO MODE PVDD (V) Figure 30. Power Dissipation vs. Output Power, 12 V, 6 , Stereo Mode, Both Channels Driven 3 Figure 33. Output Power vs. PVDD, Mono Mode, THD + N, 20 dB 30 3 4 25 OUTPUT POWER (W) 2 20 6 8 10 PDISS 15 1 5 0 1 2 3 4 5 6 7 8 9 10 11 12 06673-031 POUT PER CHANNEL STEREO MODE PVDD (V) Figure 31. Power Dissipation vs. Output Power, 12 V, 8 , Stereo Mode, Both Channels Driven Figure 34. Output Power vs. PVDD, Mono Mode, THD + N, 40 dB Rev. 0 | Page 13 of 24 06673-034 0 0 9 10 11 12 13 14 15 06673-033 0 0 9 10 11 12 13 14 15 06673-032 0 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 160 ADAU1590 25 100 90 20 80 3 4 OUTPUT POWER (W) 70 EFFICIENCY (%) 15 06673-035 15 6 10 8 60 50 40 30 5 20 10 0 2 4 6 8 10 12 14 16 18 20 06673-037 0 9 10 11 12 PVDD (V) 13 14 0 OUTPUT POWER (W) Figure 35. Output Power vs. PVDD, Mono Mode, THD + N, 60 dB 90 80 70 EFFICIENCY (%) Figure 37. Efficiency vs. Output Power, Mono Mode, 12 V, 4 60 50 40 30 20 10 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 06673-036 0 OUTPUT POWER (W) Figure 36. Efficiency vs. Output Power, Mono Mode, 12 V, 3 Rev. 0 | Page 14 of 24 ADAU1590 THEORY OF OPERATION OVERVIEW The ADAU1590 is a 2-channel high performance switching audio power amplifier. Each of the two - modulators converts a single-ended analog input into a 2-level PDM output. This PDM pulse stream is output from the internal full differential power stage. The ADAU1590 has built-in circuits to suppress the turn-on and turn off pop and click. The ADAU1590 also offers extensive thermal and overcurrent protection circuits. feature allows the user to adjust the slicer to the desired value and to limit the output power. For input signals higher than the set threshold, the slicer clips the input signal to the modulator. This adds distortion due to clipping of the signal input to the modulator. This is especially helpful in applications where the output power available needs to be reduced instead of reducing the supply voltage. Figure 38 is a plot showing THD + N vs. the input level at 0 dB PGA, 12 V, and 6 , and demonstrates the difference between a device with and without the slicer. 0 -5 -10 -15 -20 -25 -30 -35 -40 -45 -50 -55 -60 -65 -70 -75 -80 -85 -90 -95 -100 SLICER 1.1V SLICER 1.17V SLICER 1.24V SLICER 1.32V SLICER DISABLED MODULATOR The modulator is a 5th-order - with feedback from the power stage connected internally. This helps reduce the external connections. The 5th-order modulator switches to a lower order near full-scale inputs. The modulator gain is optimized at 19 dB for 15 V operation. The - modulator outputs a pulse density modulation (PDM) 1-bit stream, which does not produce distinct sharp peaks and harmonics in the AM band like conventional fixed-frequency PWM. The - modulators require feedback to generate PDM stream with respect to the input. The feedback for the modulators comes from the power stage. This helps reduce the nonlinearity in the power stages and achieve excellent THD + N performance. The feedback also helps in achieving good PSRR. In the ADAU1590, the feedback from the power stage is internally connected. This helps reduce the external connections for ease in PCB layout. The - modulators operate in a discrete time domain and Nyquist frequency limit, which is half the sampling frequency. The modulator uses the master clock of 12.288 MHz. This is generated by dividing the external clock input by 2. This sets the fS/2 around 6.144 MHz. This is sufficient for the audio bandwidth of 22 kHz. The modulator shapes the quantization noise and transfers it outside the audio band. The noise floor rises sharply above 20 kHz. This ensures very good signal-tonoise ratio (SNR) in the audio band of 20 kHz. The 6.144 MHz bandwidth allows the modulator order to be set around the 5th order. The modulator uses proprietary dynamic hysteresis to reduce the switching rate or frequency to around 700 kHz. This reduces the switching losses and achieves good efficiency. The dynamic hysteresis helps the modulator to continuously track the change in PVDD and the input level to keep the modulator stable. THD + N (dB) 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 INPUT (V rms) Figure 38. THD + N vs. Input Level @ PGA = 0 dB, 12 V Figure 39 depicts the typical output power vs. input at different slicer settings. 12.0 11.5 11.0 10.5 10.0 9.5 9.0 8.5 8.0 7.5 7.0 6.5 6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 SLICER DISABLED SLICER 1.32V SLICER 1.24V SLICER 1.17V SLICER 1.10V OUTPUT POWER (W) 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 INPUT (V rms) Figure 39. Typical Output Power vs. Input, at Different Slicer Settings SLICER The ADAU1590 has a built-in slicer block following the PGA and before the modulator. The slicer block is essentially a hard limiter included for limiting the input signal to the modulator. This, in turn, limits the output power at a given supply voltage. The slicer in the ADAU1590 is normally inactive at lower input levels but is activated as soon as the peak input voltage exceeds the set threshold. The threshold can be set externally by connecting a resistor from SLC_TH (Pin 24) to ground. This From Figure 39, it can be seen that the slicer effectively reduces the output power depending on its setting. Internally, the slicer block receives the input from the PGA. Figure 40 shows the block for slicer threshold adjust, SLC_TH (Pin 24). Rev. 0 | Page 15 of 24 06673-039 06673-038 ADAU1590 VCM GAIN 50k SLICER_LEVEL VTH PIN 24 (SLC_TH) The gain of the amplifier is set internally using feedback resistors optimized for 12 V nominal operation. The typical gain values are tabulated in Table 1. The typical gain is 17 dB with PGA set to 0 dB. PGA0 (Pin 14) and PGA1 (Pin 13) are used for setting the desired gain. The gain can be set according to Table 10. Note that the amplifier full-scale input level changes as per the PGA gain setting. Table 10. Gain Settings REXTERNAL 06673-040 Figure 40. Block for Slicer Threshold Adjust, SLC_TH The slicer threshold can be set externally using a resistor as follows: VTH = (AVDD/2) x (50 k/50 k + REXTERNAL) where: AVDD = 3.3 V typical. VTH is the voltage threshold at which the slicer is activated. The following equation can be used to calculate the input signal at which the slicer becomes active: VIN RMS = VTH 1.414 x 0.9 PGA1 (Pin 13) 0 0 1 1 PGA0 (Pin14) 0 1 0 1 PGA Gain (dB) 0 6 12 18 Amplifier Gain (dB) 17 23 29 35 Full-Scale Input Level (VRMS) 1 0.5 0.25 0.125 PROTECTION CIRCUITS The ADAU1590 includes comprehensive protection circuits. It includes thermal warning, thermal overheat, and overcurrent or short-circuit protection on the outputs. The ERR and OTW outputs are open drain and require external pull-up resistors. The outputs are capable of sinking 10 mA. The open-drain outputs are useful in multichannel applications where more than one ADAU1590 is used. The error outputs of multiple ADAU1590s can be OR'ed to simplify the system design. The logic outputs of the error flags ease the system design of using a microcontroller. Therefore, for AVDD = 3.3 V typical and VTH = 1.1 V, REXTERNAL = 24.9 k VIN RMS = 0.864 V Thus, the slicer is activated at and above 0.864 VIN RMS. This feature allows the user to set the slicer and, in turn, reduces the output power at a given supply voltage.To disable the slicer, SLC_TH should be connected to AGND. Table 9 shows the typical values for REXTERNAL. Table 9. Typical REXTERNAL Values VTH (V) 1.1 1.17 1.24 1.32 REXTERNAL (k) 24.9 20.5 16.5 12.4 VIN RMS (V) 0.864 0.919 0.974 1.037 THERMAL PROTECTION Thermal protection in the ADAU1590 is categorized into two error flags: one as thermal warning and the other as thermal shutdown. When the device junction temperature reaches near 135C (5C), the ADAU1590 outputs a thermal warning error flag by pulling OTW (Pin 10) low. This flag can be used by the microcontroller in the system for indication to the user or can be used to lower the input level to the amplifier to prevent thermal shutdown. The device continues operation until shutdown temperature is reached. When the device junction temperature exceeds 150C, the device outputs an error flag by pulling ERR (Pin 9) low. This error flag is latched. To restore the operation, MUTE (Pin 15) needs to be toggled to low and then to high again. POWER STAGE The ADAU1590 power stage comprises a high-side PMOS and a low-side NMOS. The typical RDS-ON is ~300 m. The PMOSNMOS stage does not need an external bootstrap capacitor and simplifies the high-side driver design. The power stage also has comprehensive protection circuits to detect the faults in typical applications. See the Protection Circuits section for further details. OVERCURRENT PROTECTION The overcurrent protection in the ADAU1590 is set internally at a 5 A peak output current. The device protects the output devices against excessive output current by pulling ERR (Pin 9) low. This error flag is latched. To restore the normal operation, MUTE (Pin 15) needs to be toggled to low and then to high again. The error flag is useful for the microcontroller in the system to indicate abnormal operation and to initiate the audio MUTE sequence. The device senses the short-circuit condition Rev. 0 | Page 16 of 24 ADAU1590 on the outputs after the LC filter. Typical short-circuit conditions include shorting of the output load, and shorting to either PVDD or PGND. device operation that is safely below the shutdown temperature of 150C and allows the amplifier to recover itself without the need for microcontroller intervention. UNDERVOLTAGE PROTECTION The ADAU1590 is also comprised of an undervoltage protection circuit, which senses the undervoltage on PVDD. When the PVDD supply goes below the operating threshold, the output FETs are turned to a high-Z condition. In addition, the device issues an error flag by pulling ERR low. This condition is latched. To restore the operation, MUTE (Pin 15) needs to be toggled to low and then to high again. Option 2: Using ERR Option 2 is similar to Option 1 except the ERR pin is tied to MUTE instead of OTW. See the circuit in Figure 42. ADAU1590 DVDD R1 100k ERR 9 C1 47F MUTE 15 D1 1N4148 TO MUTE LOGIC INPUT CLOCK LOSS DETECTION The ADAU1590 includes a clock loss detection circuit. In case the master clock to the part is lost, the ERR flag is set. This condition is latched. To restore operation, MUTE needs to be toggled low and high again. Figure 42. Option 2 Schematic for Autorecovery AUTOMATIC RECOVERY FROM PROTECTIONS In certain applications, it is desired for the amplifier to recover itself from thermal protection without the need for system microcontroller intervention. The ADAU1590 thermal protection circuit issues two error signals for this purpose: one a thermal warning (OTW) and the other a thermal shutdown (ERR). With the two error signals, there are two options available for using the protections: * * Option 1: Using OTW Option 2: Using ERR In this case, the part goes into shutdown mode due to any of the error generating events like output overcurrent, overtemperature, missing PVDD or DVDD, or clock loss. The part recovers itself based on the same circuit operation in Figure 41. However, if the part goes into error mode due to overtemperature, then the device would have reached its maximum limit of 150C (15C to 20C higher than Option 1). If it goes into error mode due to an overcurrent from a short circuit on the speaker outputs, then the part keeps itself recycling on and off until the short circuit is removed. It is possible that, with this operation, the part is subjected to a much higher temperature and current stress continuously. This, in turn, reduces the part's reliability in the long term. Therefore, using Option 1 for autorecovery from thermal protection and using the system microcontroller to indicate to the user of an error condition is recommended. The following sections provide further details of these two options. Option 1: Using OTW The OTW pin is pulled low when the die temperature reaches 130C to 135C. This pin can be wired to MUTE as shown in Figure 41, using an RC circuit. ADAU1590 DVDD R1 100k OTW 10 C1 47F MUTE 15 MUTE AND STDN The MUTE and STDN pins are 3.3 V logic-compatible inputs used to control the turn-on/turn-off for ADAU1590. The STDN input is active low when the STDN pin is pulled low and the device is in its energy saving mode. The modulator is inactive and the power stage is in high-Z state. The high logic level input on the STDN pin wakes up the device. The modulator is running internally but the power stage is still in high-Z state. When the MUTE pin is pulled high, the power stage becomes active with a soft turn-on to avoid the pop and clicks. The low level on the MUTE pin disables the power stage and is recommended to be used to mute the audio output. See the Power-Up/Power-Down Sequence section for more details. D1 1N4148 TO MUTE LOGIC INPUT Figure 41. Option 1 Schematic for Autorecovery The low logic level on OTW also pulls down the MUTE pin. The bridge is shut down and starts cooling or the die temperature starts reducing. When it reaches around 120C, the OTW signal starts going high. While this pin is tied to a capacitor with a resistor pulled to DVDD, the voltage on this pin starts rising slowly towards DVDD. When it reaches the CMOS threshold, MUTE is deasserted and the amplifier starts functioning again. This cycle repeats itself depending on the input signal conditions and the temperature of the die. This option allows 06673-041 Rev. 0 | Page 17 of 24 06673-042 ADAU1590 POWER-UP/POWER-DOWN SEQUENCE Figure 43 shows the recommended power-up sequence for the ADAU1590. AVDD/DVDD STDN PVDD AVDD/DVDD PVDD tINT INTERNAL MUTE tWAIT STDN MUTE tINT INTERNAL MUTE OUTx+/OUTx- PVDD/2 tWAIT MUTE PVDD/2 OUTx+/OUTx- AVDD/2 AINx tPDL-H AINx AVDD/2 tINT = 650ms @ 24.576MHz CLOCK tWAIT < TINT NOTES 1. INTERNAL MUTE IS INTERNAL TO CHIP. 06673-044 NOTES 1. INTERNAL MUTE IS INTERNAL TO CHIP. Figure 43. Recommended Power-Up Sequence The ADAU1590 has a special turn-on sequence that consists of a fixed internal mute time during which the power stage does not start switching. This internal mute time depends on the master clock frequency and is 650 ms for a 24.576 MHz clock. Also, the internal mute overrides the external MUTE and ensures that the power stage does not switch on immediately even if the external MUTE signal is pulled high in less than 650 ms after STDN. The power stage starts switching only after 650 ms plus a small propagation delay of 200 s has elapsed and after MUTE is deasserted. Therefore, it is recommended to ensure that tWAIT > tINT to prevent the pop and click during power-on. Ensure that the MUTE signal is delayed by at least tWAIT seconds after STDN. This time is approximately 10 times the charging time constant of the input coupling capacitor. For example, if the input coupling capacitor is 4.7 F, the time constant is T = R x C = 20 k x 4.7 F = 94 ms Therefore, tWAIT = 10 x T = 940 ms ~ 1 sec. tWAIT is needed to ensure that the input capacitors are charged to AVDD/2 before turning on the power stage. When tWAIT < tINT, the power stage does not start switching until 650 ms has elapsed after STDN (see Figure 44). However, note that this method does not ensure pop-and-click suppression because of less than recommended or insufficient tWAIT. 06673-043 tINT = 650ms @ 24.576MHz CLOCK tPDL-H = 200s tWAIT = 10 x RIN x CIN Figure 44. Power-Up Sequence, tWAIT < tINT The ADAU1590 uses three separate supplies: AVDD (3.3 V analog for PGA and modulator), DVDD (3.3 V digital for control logic and clock oscillator), and PVDD (9 V to 18 V power stage and level shifter). Separate pins are provided for the AVDD, DVDD, and PVDD supply connections, as well as AGND, DGND, and PGND. In addition, the ADAU1590 incorporates a built-in undervoltage lockout logic on DVDD as well as PVDD. This helps detect undervoltage operation and eliminates the need to have an external mechanism to sense the supplies. The ADAU1590 monitors the DVDD and PVDD supply voltages and prevents the power stage from turning on if either of the supplies are not present or are below the operating threshold. Therefore, if DVDD is missing or below the operating threshold, for example, the power stage does not turn on, even if PVDD is present, or vice versa. Because this protection is only present on DVDD and PVDD and not on AVDD, shorting both AVDD and DVDD externally or generating AVDD and DVDD from one power source is recommended. This ensures that both AVDD and DVDD supplies are tracking each other and avoids the need to monitor the sequence with respect to PVDD. This also ensures minimal pop and click during power-up. When using separate AVDD and DVDD supplies, ensure that both supplies are stable before unmuting or turning on the power stage. Similarly, during shutdown, pulling MUTE to logic low before pulling STDN down is recommended. However, where a fault event occurs, the power stage shuts down to protect the part. In this case, depending on the signal level, there is some pop at the speaker. Rev. 0 | Page 18 of 24 ADAU1590 To shut down the power supplies, it is highly recommended to mute the amplifier before shutting down any of the supplies. After MUTE is shut down, shut down the supplies in the following order: PVDD, DVDD, then AVDD. Where AVDD and DVDD are generated from a single source, turn PVDD off before DVDD and AVDD, and after issuing MUTE. The amount of pop at the turn-on depends on tWAIT, which in turn depends on the values of CREF and CIN. The following section describes how to select the value for the CREF and CIN. SELECTING VALUE FOR CREF AND CIN The CREF is the capacitor used for filtering the noise from AVDD on VREF. VREF is used for the biasing of the internal analog amplifier as well as the modulator. Therefore, care must be taken to ensure that the recommended minimum value is used. The minimum recommended value for CREF is 4.7 F. CIN is the input coupling capacitor and is used to decouple the inputs from the external dc. The CIN value determines the low corner frequency of the amplifier. It can be determined from the following equation: f LOW = 1 2 x x R IN x C IN DC OFFSET AND POP NOISE This section describes the cause of dc offset and pop noise during turn-on/turn-off. The turn-on/turn-off pop in amplifiers depend mainly on the dc offset, therefore, care must be taken to reduce the dc offset at the output. The first stage of ADAU1590 has an inverting PGA amplifier, as shown in Figure 45. CHANGES WITH PGA SETTING RFB CIN AINx RIN TO NEXT STAGE VREF CREF VMIS 06673-045 RSOURCE where: fLOW is the low corner frequency (-3 dB). RIN is the input resistance (20 k). CIN is the input coupling capacitor. Note that RIN = 20 k, provided that RSOURCE is <1 k. If RSOURCE is sizable with respect to RIN, it also must be taken into account in calculation. From the preceding equation, fLOW can be found for the desired frequency response. The recommended value for CIN is 2.2 F, giving fLOW = 3.6 Hz, and should keep 20 Hz roll-off within -0.5 dB. However, if a higher than recommended CIN value is used for better low frequency response, care must be taken to ensure that appropriate tWAIT is used. See the Power-Up/Power-Down Sequence section for more details. Figure 45. Input Equivalent Circuit where: RIN = 20 k, fixed internally. RFB is the gain feedback resistor (value depends on the PGA setting). RSOURCE is the source resistance. CIN is the input coupling capacitor (2.2 F typical). CREF is the filter capacitor for VREF. VREF is the analog reference voltage (AVDD/2 typical). VMIS is the dc offset due to mismatch in the op amp. As shown in Figure 45, the dc offset at the output can be due to VMIS (the dc offset from mismatch in the op amp) and due to leakage current of the CIN capacitor. Normally, the offset due to leakage current in the CIN is less and can be ignored compared to VMIS. The VMIS is mainly responsible for the dc offset at the output. The ADAU1590 uses special self-calibration or a dc offset trim circuit, which controls the dc offset (due to VMIS) to within 3 mV. The VMIS can vary for each part as well as for voltage and temperature. The trim circuit ensures that the offset is limited within specified limits and provides virtually pop-free operation every time the part is turned on. However, care must be taken while unmuting or during the power-up sequence. During the initial power-up, CIN and CREF are charging to AVDD/2 and, during this time, there can be dc offset at the output (see Figure 45). This depends on the PGA gain setting. The dc offset is multiplied by the PGA gain setting. If the amplifier is kept in mute during this charging and self-trimming event for the recommended tWAIT time, the dc offset at the output remains within 3 mV. For more details on tWAIT, refer to the Power-Up/Power-Down Sequence section. MONO MODE The ADAU1590 mono mode can be enabled by pulling MO/ST (Pin 11) to logic high. In this mode, the left channel input and modulator is active and feeds PWM data to both the left and right power stages. However, the respective power FETs need to be connected externally for higher current capability. That is, connect OUTL+ with OUTR+ and OUTL- with OUTR-. The mono mode gives the capability to drive lower impedance loads without invoking current limit. However, the output power is limited by PVDD and temperature limits. See the typical application schematic in Figure 47 for details. POWER SUPPLY BYPASSING Because Class-D amplifiers utilize high frequency switching, care must be taken to bypassing the power supply. For reliable operation, using 100 nF ceramic surface-mount capacitors for the PVDD and PGND pins is recommended. The minimum of two capacitors are needed: one between Pin 45/Pin 46 (PVDD) and Pin 47/Pin 48 (PGND), the other between Pin 39/ Pin 40 (PVDD) and Pin 37/Pin 38 (PGND). In addition, these Rev. 0 | Page 19 of 24 ADAU1590 must be placed very close to the respective pins with direct connection. This is important for reliable and safe operation of the device. One additional 1 F capacitor in parallel to the 100 nF capacitor is also recommended. A bulk bypass capacitor of 470 F is also recommended to remove the low frequency ripple due to load current. Similarly, one 100 nF capacitor is recommended between each DVDD/DGND and AVDD/AGND. These capacitors also must be placed close to their respective pins with direct connection. Option 3: Using an External Clock The ADAU1590 can be provided with an external clock of 24.576 MHz at the XTI pin. The logic level for the clock input should be in the range of 3.3 V and 50% typical duty cycle. For systems using multiple ADAU1590s, it is recommended to use only one clock source if the ADAU1590s share the same power supply to prevent the beat frequencies of asynchronous clocks from appearing in the audio band. Multiple ADAU1590s can be connected in a daisy chain by providing or generating a master clock from one ADAU1590 and subsequently connecting its XTO output to the XTI input of the next ADAU1590, and so on. However, using a simple logic buffer between the XTO pin of one ADA1590 to the XTI pin of the next ADAU1590 is recommended. Because the clock output is now buffered, it can be connected to the XTI inputs of the remaining ADAU1590s, depending on the fanout capability of the logic buffer used. CLOCK The ADAU1590 uses 24.576 MHz for the master clock, which is 512 x fS (fS = 48 kHz). There are several options for providing the clock. Option 1: Using a Quartz Crystal A quartz crystal of 24.576 MHz frequency can be connected between the XTI and XTO pins using two load capacitors suitable for the crystal oscillation mode. Option 2: Using a Ceramic Resonator The ADAU1590 can also be used with ceramic resonators similar to crystal by using the XTI and XTO pins. Rev. 0 | Page 20 of 24 ADAU1590 APPLICATIONS INFORMATION 3.3V PVDD 100nF 100nF 100nF 100nF 1F 470F TEST3 AVDD ANALOG INPUT LEFT 2.2F AINL 100k OUTL+ C1 L1 SLC_TH R3 OUTL- DVDD PVDD L2 C2 VREF 4.7F 100nF OUTR+ L3 C3 ADAU1590 ANALOG INPUT RIGHT 2.2F AINR 100k OUTR- C4 L4 STDN SYSTEM LOGIC MICROCONTROLLER MUTE ERR OTW TEST12 TEST13 MO/ST TEST0 TEST1 TEST8 TEST9 AGND DGND 24.576MHz CRYSTAL OR RESONATOR PGND XTO XTI Figure 46. Typical Stereo Application Circuit Table 11. R3--Slicer Threshold Resistor VTH (V) 1.1 1.17 1.24 1.32 R3 (k) 24.9 20.5 16.5 12.4 Table 12. Output Filter Component Values Load Impedance () 4 6 8 Inductance L1 to L4 (H) 10 15 22 Capacitance C1 to C4 (F) 1.5 1 0.68 Rev. 0 | Page 21 of 24 06673-046 ADAU1590 3.3V PVDD 100nF 100nF 100nF 100nF 1F 470F MO/ST TEST3 AVDD ANALOG INPUT LEFT 2.2F AINL 100k OUTL+ C1 L1 SLC_TH R3 OUTL- DVDD PVDD L2 C2 VREF 4.7F 100nF OUTR+ ADAU1590 ANALOG INPUT RIGHT 2.2F AINR 100k OUTR- STDN SYSTEM LOGIC MICROCONTROLLER MUTE ERR OTW TEST12 TEST13 TEST0 TEST1 TEST8 TEST9 AGND DGND 24.576MHz CRYSTAL OR RESONATOR PGND XTO XTI Figure 47. Typical Mono Application Circuit For component values, refer to the stereo application circuit in Figure 46. Rev. 0 | Page 22 of 24 06673-047 ADAU1590 OUTLINE DIMENSIONS 7.00 BSC SQ 0.60 MAX 0.60 MAX 37 36 0.30 0.23 0.18 48 1 PIN 1 INDICATOR PIN 1 INDICATOR TOP VIEW 6.75 BSC SQ EXPOSED PAD (BOTTOM VIEW) 5.25 5.10 SQ 4.95 0.50 0.40 0.30 25 24 12 13 0.25 MIN 5.50 REF 1.00 0.85 0.80 12 MAX 0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM 0.50 BSC SEATING PLANE 0.20 REF COPLANARITY 0.08 COMPLIANT TO JEDEC STANDARDS MO-220-VKKD-2 Figure 48. 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 7 mm x 7 mm Body, Very Thin Quad (CP-48-1) Dimensions shown in millimeters 0.75 0.60 0.45 1.00 REF SEATING PLANE 1.20 MAX 48 1 9.20 9.00 SQ 8.80 37 36 PIN 1 37 36 BOTTOM VIEW (PINS UP) 48 1 TOP VIEW (PINS DOWN) EXPOSED PAD 12 13 25 24 25 24 12 13 5.10 SQ 1.05 1.00 0.95 7.20 7.00 SQ 6.80 0.20 0.09 7 3.5 0 VIEW A 0.15 0.05 0.50 BSC LEAD PITCH 0.08 MAX COPLANARITY 0.27 0.22 0.17 ROTATED 90 CCW COMPLIANT TO JEDEC STANDARDS MS-026-ABC Figure 49. 48-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP] (SV-48-5) Dimensions shown in millimeters ORDERING GUIDE Model ADAU1590ACPZ 1 ADAU1590ACPZ-RL1 ADAU1590ACPZ-RL71 ADAU1590ASVZ1 ADAU1590ASVZ-RL1 ADAU1590ASVZRL71 1 Temperature Range -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C 042407-A VIEW A Package Description 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ], 13" Tape and Reel 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ], 7" Tape and Reel 48-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP] 48-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP], 13" Tape and Reel 48-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP], 7" Tape and Reel Package Option CP-48-1 CP-48-1 CP-48-1 SV-48-5 SV-48-5 SV-48-5 Z = RoHS Compliant Part. Rev. 0 | Page 23 of 24 ADAU1590 NOTES (c)2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06673-0-5/07(0) Rev. 0 | Page 24 of 24 |
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